The present invention relates generally to semiconductor devices and methods, and more particularly, to an integrated circuit architecture and test methodology for use in fabricating and testing mixed signal integrated circuit devices.
Over the last several decades, "design for testability" techniques have been defined that allow integrated circuit logic to be completely controllable and observable. Typical techniques are described in "Mixed-signal testing using analog scan design," by Richard Hulse, and "Toward an analog and mixed-signal test bus standard," by Steve Dollens et al. published in Analog & Mixed Signal Design Conference Proceedings, Oct. 28-30, 1992, at pages 244 and 204, respectively. These well-known techniques include full/partial scan, built-in self test, and massive observability, for example. Unfortunately, these techniques are directed toward digital circuitry and provide no means to allow adequate testing of analog or nonvolatile structures. The concept of testability is important and cannot be overlooked for mixed-signal integrated circuit chips. A new technique is therefore required to allow complete testing of digital, analog, and nonvolatile circuits on the same chip.
Lack of a structured test approach for mixed-signal devices, and the drive to produce high performance, small die size chips, has forced an "ad-hoc" approach to proliferate in the industry. Although this approach requires little silicon overhead and has a minimal performance impact, it may result in chips that have not been sufficiently tested. This approach is not adequate for mixed signal integrated circuit devices. The design of such chips tend not to be die-size and performance-driven; instead, the focus is to quickly provide operational, reliable circuits. Therefore, it is necessary to provide a test methodology to address this changing environment.
The conventional "ad-hoc" approach is typified by the use of integrated standard digital test structures in the logic and special test pads and/or extra circuitry to allow for controllability and observability of the analog and nonvolatile circuits. Unfortunately, this approach is not well structured, documented, or consistent in the design community, and typically translates into unpredictable, higher test development costs.
The assignee of the present invention is currently developing a customized mixed signal application specific integrated circuit (ASIC) design system. This system is cell based and is designed to lessen circuit development time for first-time working silicon. The initial cell library is based upon a nonvolatile CMOS process and is comprised of analog, digital, nonvolatile memory (EEPROM), mask memory (ROMs), volatile memory (RAMs), and microcontroller cells. The design environment includes options that permit designers to implement ASIC designs, including schematic capture, simulation, and test vector generation.
It is therefore an objective of the present invention to provide an architecture and test method for mixed signal integrated circuits that permits operability and testing of the circuits. It is a further objective of the present invention to provide a mixed signal integrated circuit architecture and a test methodology that is integrated into the above-cited ASIC design system.